| 摘要 |
<p>A decoder circuit of a semiconductor memory device includes a plurality of logic gates each constituted by a load transistor (Q<Sub>3</Sub>) and drive transistors (Q<Sub>o</Sub>, Q<Sub>i</Sub>, Q<Sub>2</Sub>) generating a line selection signal corresponding to input address signals (a<Sub>o</Sub>, a<Sub>1</Sub>, a<Sub>2</Sub>), and a power source control circuit (11) for controlling the power source voltage (V<Sub>cc</Sub>) supplied to the logic gates in accordance with a mode designation signal (0,0) which is a normal mode signal or an all selection mode signal.</p><p>When the all selection mode signal is input to the power source control circuit (11), the all selection mode state of the decoder circuit is obtained by pulling down the power source voltage (Vcc) supplied to the logic gates.</p> |
