Semiconductor memory device in form of shift register with two-phase clock signal supply.

摘要

A semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the two-phase clock signal lines (P1) is connected to even order shift register elements (0,2,4) of the shift register, and the other of the two-phase clock signal lines (P2) is connected to odd order shift register elements (1,3) shift register. Each of the shift register elements includes an output node (S(Jn-1), S(Jn),....), a gate (206) connected between the output node and a clock signal supplying node, a charge-up circuit (204, 205) responsive to the output signal of the preceding shift register element for preliminarily charging a control node (N.) of the gate, and a discharge circuit (203) responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.