| 摘要 |
PURPOSE:To improve the reliability by delaying an energization of a coil of each phase longer than the turning OFF time of a transistor, thereby preventing the transistor from damaging. CONSTITUTION:The first phase control latch circuit 18 loads phase control data from a bus line 19 when an input of a data write signal S1 is presented, and latches it. Phase control signals are supplied from output terminals Q1, Q2, Q3, Q4 to the second phase output latch circuit 20, and supplied to four AND gates 21, 22, 23, 24. A monostable circuit 25 outputs a data write signal S2 to the second phase output latch circuit 20 after the prescribed time is elapsed by the input of a signal S1. The data of the second phase output latch circuit 20 is supplied through AND gates 21, 22, 23, 24 to transistors 12a, 12b, 12c, and 12d. |
