Intermittently operated frequency synthesizer having suppressed frequency instability

摘要

A frequency synthesizer having an intermittently operated PLL circuit in which power is intermittently applied to a prescaler to reduce power consumption. The PLL circuit is operated such that fluctuations in the frequency synthesizer output frequency do not occur. This stability in the output frequency results from selectively providing signals to the phase comparator within the PLL circuit only during a time period beginning after power is applied to the prescaler and ending before power is removed from the prescaler.