发明名称 VIDEO SIGNAL PROCESSOR
摘要 PURPOSE:To reduce memory capacity and to simplify the constitution by inputting write data and a write address to a memory part in the fly-back time of a slave picture video signal after the write data and the write address are provisionally held in a latch part while data is transferred to a shift register from a memory in the fly-back time of a master picture video signal. CONSTITUTION:Each bit of the write data during a transfer period DELTAtau is held in latches 10a-10n, while the write address during the transfer period DELTAtau is held in a latch 13. The write address held in the latch 13 accesses the memories 10a-10n at random until a transfer timing pulse is outputted in the fly-back time Sb of the slave picture video signal, and each bit of the write data during the transfer period DELTAtau, which is held in the latches 10a-10n, is written at the write address held in the latch 13. Accordingly each write data during a scan period Sa including the transfer period can be written in a memory part 14 without omission.
申请公布号 JPS61265979(A) 申请公布日期 1986.11.25
申请号 JP19850108759 申请日期 1985.05.20
申请人 SANYO ELECTRIC CO LTD 发明人 OSANAWA KAZUO;YANASE HIDEJI
分类号 H04N5/265;H04N5/45 主分类号 H04N5/265
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