COINCIDING AND CONTROLLING SYSTEM FOR MAIN STORAGE

摘要

PURPOSE:To eliminate the buffer invalidation BI processing by turning on a flag for the invalidation of a buffer memory in a continuous store or distance store mode against a vector unit. CONSTITUTION:The start address of a main storage is set tot a logical address holding register LAHRA. While the distance amount is set to an indirect address register IARA. Furthermore the vector length showing the number of elements is set to a vector length register VLR. The outputs of these registers are processed by shift registers ASR0 and ASR1 and an adder respectively. When a vector processor gives a continuous store access or a distance access to the main storage, the flag for invalidation processing of a buffer memory is turned on in case data are stored over the boundary of the data block size of the buffer memory or data are stored finally within said boundary.