| 摘要 |
PURPOSE:To avoid the invalid processing of another processor by providing an interruption request circuit at the interruption receiving side and producing an interruption only to the processor at the remote side when the information is exchanged between processors. CONSTITUTION:A CPU #1 unit 1 writes the information to be transmitted to an information exchange area C2 of a shared memory 9 and executes an interruption instruction OUT-02H against a CPU #2 unit 2. The unique value discriminating CPU#1-CPU#3 is set previously to a setting circuit 10. For instance, 02H is set with the unit 2. Therefore the 02H is delivered to an address line 11 and the coincidence signal is delivered only from a coincidence detecting signal 13 of the unit 2. Then an interruption signal INT is produced as the output of an AND circuit 14 which secures an AND with an OUT signal 12 produced by an interruption instruction. While no interruption signal is produced for units 1 and 2.
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