| 摘要 |
PURPOSE:To swiftly execute the synchronizing by forcively changing the frequency division ratio of a counter when the synchronizing is not yet complete and changing the period of output to make short the interval until when a reference-period signal and the phase of the counter's output coincide with each other. CONSTITUTION:A video signal input 1 is inputted to a vertical synchronizing separator circuit 2, and a V-signal (REF-V) is generated. A pulse generator 3 generates a pulse synchronized with this V-signal, and supplies it to an AND gate 14 and a D-REF 15. Meanwhile, a clock signal generated by a clock signal generator 4 is counted down with a period of V/16 by a counter 5, and is inputted to a counter 6. The counter 6 outputs in parallel the outputs frequency- divided to 1/2-1/16, and inputs them to an AND gate 11. The output from the gate 11 triggers an MM 12, and triggers an MM 13 with a prescribed time- delay. A pulse signal synchronized with the out REF-V of the MM 13 is supplied to the AND gate 15 whose output resets the counters 5 and 6. The synchronizing operation is thus executed. |
