| 摘要 |
PURPOSE:To suppress a short channel effect by coating an insulating layer on a substrate to form a gate in a recess on the substrate, and then performing the step of forming a groove on the substrate through the insulating layer on a gate electrode forming region to reduce source and drain resistance. CONSTITUTION:A silicon oxide layer 2, a silicon nitride layer 3 as the first insulating layer and a resist 4 are sequentially coated on a P-type silicon substrate 1, and the resist 4 of the gate formed part is opened by a lithographic method. With the resist 4 as a mask it is etched by an RIE method to form a groove 5 which arrives at the substrate 1. The resist 4 is removed, oxidized to form the second insulating layer 6, a polysilicon layer 7 is coated, and a silicon nitride layer 3 is exposed by etching. After the layer 7 is removed, arsenic ions are implanted to form N<+> type source 1S and drain 1D. |
