| 摘要 |
PURPOSE:To prevent the destruction of a DRAM contents due to a system reset signal by obtaining the synchronization between the timing for the applica tion of the system reset signal and an idle time. CONSTITUTION:The system reset signal D which is produced with an optional timing is gated by a gate circuit 2 for the system reset signal. The signal D is transmitted at a time point when the system idle signal C extracted out of signals A and B by a system idle state deciding circuit 1 is set at H and then set under an idle state. Then a system is reset with the rise of a system reset signal F serving as the output of a system reset signal shaping circuit 3. Thus the signal F is applied during the idle time when no access is given to the DRAM of the system to avoid the signal S from the destruction of the DRAM contents. |
