发明名称 |
High-performance computer system. |
摘要 |
<p>A parallel processor comprised of a plurality of processing nodes, each node including a processor and a memory. Each processor includes means for executing instructions, logic means connected to the memory for interfacing the processor with the memory and means for internode communication. The internode communication means connect the nodes to form a first array of order n having a hypercube topology. A second array of order n having nodes connected together in a hypercube topology is interconnected with the first array to form an order n+1 array. The order n+1 array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors are connected to the nodes of the arrays by means of 1/0 channels. The means for internode communication comprises a serial data channel driven by a clock that is common to all of the nodes.</p> |
申请公布号 |
EP0201797(A2) |
申请公布日期 |
1986.11.20 |
申请号 |
EP19860105879 |
申请日期 |
1986.04.29 |
申请人 |
NCUBE CORPORATION |
发明人 |
COLLEY, STEPHEN RICHARD;JURASEK, DAVID WALTER;PALMER, JOHN FRANKLIN;RICHARDSON, WILLIAM STANLEY;WILDE, DORAN KENNETH |
分类号 |
G06F15/173;(IPC1-7):G06F15/16 |
主分类号 |
G06F15/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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