发明名称 |
Self-checking, dual railed, leading edge synchronizer. |
摘要 |
<p>The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship. </p> |
申请公布号 |
EP0202085(A2) |
申请公布日期 |
1986.11.20 |
申请号 |
EP19860303561 |
申请日期 |
1986.05.09 |
申请人 |
TANDEM COMPUTERS INCORPORATED |
发明人 |
CHANDRAN, SRIKUMAR R.;WALKER, MARK S. |
分类号 |
G06F11/18;G06F1/04;G06F1/12;H03K5/00;H03K5/135;H03K5/151;(IPC1-7):H03K5/135 |
主分类号 |
G06F11/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|