发明名称 FULLY DOUBLE CONTROL SYSTEM FOR LOGICAL STRUCTURE
摘要 PURPOSE:To attain the fully double control of a logical structure by providing a data flow means which controls individually the input/output data and the request/answer signals and a control means for said data flow means to a processor which is connected to a component for communication control. CONSTITUTION:A component 1 is connected to a processor 2 consisting of an interface control part 2-1, a data flow part 2-2 and a control part 2-3. The data transmitted from the processor 2 are checked at a check part 2-12 and held by a buffer 2-13 for waiting. When a request for answer is given from the component 1, the data are informed to the component 1 via the processing of an information part 2-14. If a request for answer is given to the received data, an answer is produced at an answer transmission processing part 2-10. When a request for transmission is given from the component 1, the transmission data is produced at a transmission part 2-16 via a transfer part 2-15. The received answer is checked at an answer reception processing part 2-11. In such a way, the fully double control is possible for a logical structure.
申请公布号 JPS61262959(A) 申请公布日期 1986.11.20
申请号 JP19850106738 申请日期 1985.05.17
申请人 FUJITSU LTD 发明人 ENOKIDA MIKIYA
分类号 H04L29/08;G06F13/00;H04L13/00 主分类号 H04L29/08
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