| 摘要 |
In a device for amplifying an analog signal which is variable in amplitude and frequency, the output signal is intended to be able to be reduced continuously, using a small number of switching amplifier stages, to the lowest values without restriction due to minimum switching times which are to be adhered to. To achieve this, a series of inverter pairs (WR11, WR12; WR21, WR22...; WRn1, WRn2) which are connected on the input side in parallel or in series to a DC voltage supply source (E) is provided, each inverter being operated at a constant frequency, the first inverters (WR11, WR21, ..., WRn1) of the inverter pairs being activated with a fixed phase position in each case shifted through a phase angle @1, @2,...,@n where @k - @k-1 = constant, k = 1, 2, ... n, @O = 0, and the second inverters (WR12, WR22, ..., WRn2) of the inverter pairs being activated with the aforementioned - but in each case shifted through a control angle alpha which is directly proportional to the analog signal - phase angles @1 + alpha , @2 + alpha ,...,@n + alpha , each inverter feeds to an output transformer (T11, T12,...Tn2), the secondary windings of the transformers (T11, T12,...; Tn1, Tn2) of an inverter pair being connected in series and the latter being connected to a rectifier bridge (GR1, GR2, ... GRn) and, on the series connection of the rectifier bridges, the ... Original abstract incomplete. <IMAGE>
|
