| 摘要 |
PURPOSE:To prevent an error caused when a consecutive sign of a serial input data takes place by providing a data change point detector and a phase controller controlling a phase correction quantity so as to detect the data change point and to control the phase control quantity at each data change point. CONSTITUTION:A data change point detector 1 detects the leading and trailing of a bit of a serial input data comprising a digital pulse train and generates a pulse at the point. A phase comparator 2 detects the lead/lag of the phase of a recovered clock from that of a pulse formed by the detector 1 and gives the result to a low pass filter 4. The phase quantity controller 3 gives a phase correction quantity signal controlled by a CPU to the low pass filter 4 in matching with the pulse formed by the data change point detector 1. The low pass filter 4 receives the signal representing the phase lead/lag from the phase comparator 2, or receives the phase correction quantity signal from the comparator 3 to control a voltage controlled oscillator 5 according to the phase correction quantity in a way retarding the phase when led and advancing when lagged. |
