FRAME SYNCHRONIZING SYSTEM

摘要

PURPOSE:To make it possible to always detect a superior frame synchronization by performing the first clock signal having a prescribed frequency from the first clock signal at an PLL and detecting a frame synchronizing pattern. CONSTITUTION:An input signal 1 to which a frame synchronizing pattern performed with the clock of the first frequency is inserted is sampled at an A/D conversion circuit 12 with the clock of the second frequency that is different from the first frequency. At such a time, the clock of first frequency is performed with supplying the clock of the second frequency from a VCXO13 to a PLL18. With using the clock of the first frequency, the frame synchronizing pattern is detected from the input signal 1 at a detection circuit 5. With using the frame synchronizing pattern, the clock of the second frequency is synchronized with the input signal 1 at a frame phase detection circuit 6.