发明名称 HIGH-SPEED STACK CIRCUIT FOR RESISTER DATA
摘要 PURPOSE:To stack the data on an internal register to a RAM with use of a bit line and giving the control to an interruption routine with a small number of cycles, by extending the bit line of a memory up to the internal register of a CPU and providing a coupling part which can control the read/write on the extended bit line. CONSTITUTION:A RAM and a CPU are mounted on a single chip and connected to each other via a bus line. thus a microcomputer is formed. The bit lines BL and BL' of the RAM are extended up to the internal registers R0-R5 of a CPU. A decoder DEC which selects the word line of the RAM, a multiplexer MPC which controls the DEC, a CPU, CTL, etc. are provided to the address and data buses set between the RAM and the CPU. Then the read/write of data is controlled between the RAM and the CPU and the data on registers R0-R5 re stacked to the RAM by means of both bit lines BL and BL'. Thus the interruption routine is controlled at a high speed.
申请公布号 JPS61262922(A) 申请公布日期 1986.11.20
申请号 JP19850105572 申请日期 1985.05.17
申请人 FUJITSU LTD 发明人 YAMADA KENJI
分类号 G06F9/30;G06F7/00;G06F9/42;G06F9/46;G06F9/48;G06F12/00;G06F15/78 主分类号 G06F9/30
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