发明名称 |
Bias generator circuit. |
摘要 |
<p>@ A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.</p> |
申请公布号 |
EP0202074(A1) |
申请公布日期 |
1986.11.20 |
申请号 |
EP19860303507 |
申请日期 |
1986.05.08 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
LIU, WEI-TI |
分类号 |
H01L27/04;G05F3/20;G11C11/407;H01L21/822;H01L27/08;H01L27/092;H03K17/687;H03K19/094;(IPC1-7):G05F3/20 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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