发明名称 BUFFER CONTROL SYSTEM FOR COMMUNICATION CONTROLLING EQUIPMENT
摘要 PURPOSE:To shorten a processing time by storing a data on a processing queue in the main storage of a main processor after the processing is over and at the same time providing a table to a secondary processor to store the address of the processing queue of transmission of the data on the main storage. CONSTITUTION:A communication controller 3 consists of the main processor 1 and the secondary processor 2. The processor 2 secures the correspondence to the address of a main storage 1-2 corresponding to the processing queue stored in a buffer 1-1 after the generation of a transmission request. Then the processor 1 sets the head addresses of the corresponding addresses to the table 2-1 of the processor 2 in the order of earlier transmission. When the processor 2 receives the request of transmission from the processor 1, the processor 2 detects the first head address stored in the table 2-1 and transmits first the data on the corresponding head address of the storage 1-2 onto a circuit 4. The processor 2 repeats the transmission until all head addresses of the table 2-1 are through and informs the end of transmission to the processor 1. In such a way, the processing time is shortened with the controller 3.
申请公布号 JPS61262955(A) 申请公布日期 1986.11.20
申请号 JP19850106740 申请日期 1985.05.17
申请人 FUJITSU LTD 发明人 ISHIWATARI RYOJI
分类号 H04L29/02;G06F5/06;G06F13/00;H04L13/00 主分类号 H04L29/02
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