发明名称 SYNCHRONISM DISCRIMINATING CIRCUIT
摘要 PURPOSE:To attain ease of fault check and to prevent the deterioration of efficiency of the device by comparing a synchronism pattern prepared in advance with a synchronism pattern regenerated and synchronized with a phase locked loop circuit so as to discriminate it as to whether the synchronism is locked. CONSTITUTION:When the phase locked loop circuit is synchronized with the synchronism pattern 2, a comparator circuit 9 gives a coincidence signal ''1'' to an NOT circuit 10 as shown in solid lines in Fig. G. Thus, the output of the NOT circuit 10 remains ''0'' and an output of an AND circuit 11 remains ''0'' and a flip-flop 12 is not set. Thus, the level of a terminal C remains ''0'' as shown in solid lines in Fig. H. If the phase locked loop circuit is not synchronized with the synchronism pattern 2, the output of the comparator circuit remains ''0'' as shown in dotted lines in Fig. G. Then the output of the NOT circuit 10 goes to ''1'' and that of the AND circuit 11 goes to ''1'', and the flip-flop 12 is set. Thus, an output of the flip-flop 12 goes to ''1'' as shown in dotted lines in Fig. H and an alarm representing out of synchronism is raised from the terminal C.
申请公布号 JPS60182058(A) 申请公布日期 1985.09.17
申请号 JP19840036749 申请日期 1984.02.28
申请人 FUJITSU KK 发明人 HANAOKA YASUHIKO;OOTSUKA SATORU;MOROTO KIYOO
分类号 G11B20/10;G11B20/18 主分类号 G11B20/10
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