| 摘要 |
PURPOSE:To decrease the timing error by detecting a level of a reference clock when an input pulse is inputted and changing over a clock counted by a counter with the reference clock and its inverting clock. CONSTITUTION:A detecting circuit 3 detecting a level of the reference clock when an input pulse 1 having no synchronous relation with the reference clock is inputted, a selection circuit 4 selecting one of the reference clock and the inverting clock being the inversion of the reference clock by the output of the detection circuit, a counter 5 counting the clock outputted from the selection circuit ad a reset circuit 6 bringing the counter into the initial state when the input pulse is inputted, are provided. Further, a decode circuit 7 generating a timing pulse after a prescribed number of clocks after the input pulse is inputted by decoding the output of the counter is provided. Thus, the timing error when the input pulse is inputted until the timing pulse is outputted is kept within a half clock of the reference clock. |
