| 摘要 |
PCT No. PCT/SE82/00153 Sec. 371 Date Dec. 15, 1982 Sec. 102(e) Date Dec. 15, 1982 PCT Filed May 6, 1982 PCT Pub. No. WO82/04145 PCT Pub. Date Nov. 25, 1982.An arrangment to distribute send permission to any of the terminals in a telecommunication network when transmitting information between terminals which are connected to each other through a common ring bus controlled by a computer being located in each of the terminals. On the ring bus a signal word frame (SP) of HDLC format is circulating. The frame which is sent from any of the terminals comprises a send permission word in the form of a specific signal pattern. When one or more of the terminals connected to the bus is in a determined logic condition, that terminal receives the send permission which is first to occupy said logic state in relation to the position of the send permission frame on the loop. As soon as one of the terminals has received the send permission it transmits an abortion pattern within the frame to the bus. The frame then becomes invalid and no other terminal can have the send permission. When a terminal has finished its information transmission it retransmits the send permission frame to the bus so that a send permission again is available to all the terminals. When a terminal has nothing to send the own terminal is aborted, and the circulating send permission is looped through the terminal back to the ring bus. An address comparison logic circuit (AL) receives all the frames on a first input and compares the address field in the received frames with a fixed address (ACA) corresponding to the pattern of said send permission and generates upon equal addresses a control signal either to a first abortion generator (AG1) or a second abortion generator (AG2) depending on the logic signal state (CFR) of a second input. Said first abortion generator transmits, when activated, an abortion work (AB) within the frame to the bus. Said second abortion generator transmits, when activated, an abortion signal word (AB) within the frame towards the own terminal. A flag detection circuit (FL) detects the incoming data flow and transmits, for each received, complete flag signal pattern, a control signal to the address camparison circuit to start said comparison.
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