| 摘要 |
PURPOSE:To eliminate to consider the time of the exclusive use of a bus in the programming of each processor and to facilitate the generation of a program by performing common use control and priority control over an address/data bus by plural processors respectively. CONSTITUTION:A bus analysis control circuit 11 which analyzes requests to use the bus exclusively from processor circuits 2-5 and checks them on the basis of priority to send out a bus exclusive-use permission specifying signal consists of a bus analyzing circuit 13 and a bus control circuit 14. The bus analyzing circuit 13 stores priority information in a memory circuit 12 and each processor makes a request to use the address/data bus 1 at an optional point of time when necessary. Then, the bus analyzing circuit 13 sets a flag according to the priority level stored in the memory circuit 12 and a bus control circuit 14 confirms the contents of the memory circuit 12 to inform the processor of the bus use request having top priority among requests for which flags are set, thereby allowing the processor to use the bus. When the end of the bus use of the processor is detected, the flag for the request to use the bus is reset.
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