| 摘要 |
PURPOSE:To perform fast address conversion by adding a little hardware and to increase an input/output processor by providing a connecting device, a memory access processing request means, a memory access processing request means, the 1st bus, and the 2nd bus. CONSTITUTION:A central processor 1 performs processing corresponding to a received command. When access is attained in absolute mode wherein address conversion is not necessary, the central processor 1 sends out a received address to an address bus 10-1 as it is and the command is converted to format matching with a memory interface and outputted as command pulses 10-2, accessing a main storage device. Then, the input/output processor 3 fetches read data outputted from the main storage device to a data bus 10 10-3 in a read buffer register 3-7. At this time, a fetch instruction for the data is sent from the central processor 1 to the request control circuit 2-4 in the connecting device 2 and further sent to the memory access control part 3-3 of the input/ output processor 3 which makes the request, and the memory access control part 3-3 sends out a signal to the read buffer register 3-7.
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