发明名称 |
Constant duty cycle, frequency programmable clock generator |
摘要 |
A digital clock generator circuit which accepts a rate signal and a master clock signal and generates an output clock signal exhibiting a frequency which is programmed by the rate signal is disclosed. A constant duty cycle characteristic of the output clock signal is obtained regardless of the output clock signal's frequency. A memory element which generates the output signal is placed in one logical state when a counter portion of the present invention reaches a terminal count. The memory element is placed in an opposing logical state whenever the counter achieves 1/2 of its programmed value. A duty cycle compensator makes small timing adjustments to compensate for any truncation error which occurs in dividing the rate signal by two.
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申请公布号 |
US4623846(A) |
申请公布日期 |
1986.11.18 |
申请号 |
US19850701727 |
申请日期 |
1985.02.14 |
申请人 |
MOTOROLA, INC. |
发明人 |
LAMACCHIA, MICHAEL P. |
分类号 |
H03K21/10;(IPC1-7):H03K3/01 |
主分类号 |
H03K21/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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