发明名称 FIFO MEMORY CONTROL DEVICE
摘要 PURPOSE:To change dynamically the word length of an FiFo memory by inputting a calculating processing part inserting position changing request signal outputted from an FiFo memory dividing control circuit and providing the change-over device control circuit to control the inserting position of the calculating processing part. CONSTITUTION:An FiFo memory dividing control circuit 14, when the fully-filled information of an input FiFo memory unit group to generate within a constant time comes to be larger than the number of times of threshold set beforehand, recognizes that the word length of the input FiFo memory unit group is short, outputs the control signal to a change-over device control circuit 15, and changes a change-over device 13-2 to an (a) side and a change-over device 13-3 to a (b) side. Thus, an arithmetic processing part 2 is inserted between FiFo memory units 12-3 and 12-4. In such a same way, the circuit recognizes that when the empty information of an output FiFo memory unit group comes to be larger than the number of times of threshold, the word length of the output FiFo memory unit group is excessive, and changes the inserting position of the processing part 2 to the output terminal side.
申请公布号 JPS61259347(A) 申请公布日期 1986.11.17
申请号 JP19850100715 申请日期 1985.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAMIYAMA YUJI
分类号 G06F5/06;G06F12/00;G06F12/02;G06F12/04;G11C7/00 主分类号 G06F5/06
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