Programmable processor for digital signals - has timing circuit reconditioned by simple flip=flop circuit

摘要

The internal data bus (20) of the programmable processor is connected to the time counter (34) of the circuit. The SET-OFF signal (38) is fed to the S input of the flip-flop part (36a) of the condition circuit (36). The RESET signal (40) is gated (36b) by the Q output of the flip-flop. The gate output and the R output of the flip-flop are fed to the counter (34). The counter (34) is fed by a clock signal (fosc) via a divider circuit (42). The counter output is fed via a resistive divider (R1,R2) to an output capacitor (C).