发明名称 INTERPOLATION DEVICE FOR CLOCK SIGNAL
摘要 PURPOSE:To ensure the clock interpolation in response to a wide range of clock frequencies by deciding the omission of a clock if no subsequent clock is produced within a fixed period and producing clocks automatically until the next clock is detected in the clock cycle set immediately before said omission of the clock. CONSTITUTION:A clock cycle measuring means 11 serves as a monitor device for cycle of a reproduced clock. In addition, a clock cycle holding means 12 is provided together with a comparator 13 serving as a clock omission deciding means, a comparison coefficient setting circuit 14, an offset circuit 15 serving as an omitted clock generating means and a counter 16 for complement of 2. Thus the interpolation is possible for the omitted clock over a wide range of reproduced clock frequencies. Furthermore the value obtained by the circuit 12 and normalized by the circuit 15 within the omitted clock generating means and then counted in a complement style of 2. In such a way, the stable interpolation clocks can be produced with no disturbance produced even in an omission/ recovery mode of reproduced clock.
申请公布号 JPS61258370(A) 申请公布日期 1986.11.15
申请号 JP19850100729 申请日期 1985.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAGUCHI SUSUMU
分类号 G11B20/10;H03K5/00 主分类号 G11B20/10
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