| 摘要 |
PURPOSE:To facilitate gate array forming and IC forming and to attain high speed processing by combining a coefficient device, a gate circuit controlling an input or an output of the coefficient device in response to the state of each bit of multiplication and an adder taking the total sum of each terms so as to realize directly the multiplication by modulus. CONSTITUTION:Input/output of 8-bit parallel data are applied from a multiplicand input terminal 1, a multiplier input terminal 2 and a product output terminal 3 outputting a product as the result of multiplication. Coefficient devices 4-10 are given to them to multiply coefficients for unit and the coefficient device 4 multiplies alpha<7> to a multiplicand and the coefficient device 10 multiplies alphato the multiplicand. A control input of gate circuits 11-18 connected to the output of the coefficient devices is connected to each bit of a multiplier. Each input of an adder 19 on 8-input finite field is connected to the output of the gate circuits 11-18 an the output is connected to the terminal 3. The coefficient devices 4-10 are realized by replacement and exclusive OR of bits fundamentally.
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