| 摘要 |
PURPOSE:To smoothly carry out the information transmission between CPUs by prohibiting one CPU from making access to a memory area when the other CPU makes access to a shared memory area. CONSTITUTION:Before a CPU 1 makes access to a shared memory area 4, the area 4 is made access after a specific address is outputted to an address buffer 3. After the CPU 1 outputs the specific address to the buffer 3, when a CPU 2 tries to make access to the area 4 and outputs the address to the buffer 3, an HALT input signal 8 to the CPU 2 is activated by the buffer 3 to make the CPU 2 halt, thereby the CPU 2 is prohibited from making access to the area 4. When the CPU 1 completes the access of the area 4, a specific address is outputted to the buffer again to release the signal 8 and enable the CPU 2 to make access to the area 4. Thus, the information transmission between the CPUs can be smoothly performed.
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