SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE:To keep the degree of freedom in wiring from being reduced by a method wherein a latch-up phenomenon is obstructed by parasitic PNP transistors constituted by the first P-type diffused regions, an N-type semiconductor substrate and a P-type well region; and polycrystalline silicon gates are provided between the second P-type semiconductor substrate and between the P-type well region and the second N-type diffused region. CONSTITUTION:The second N-type diffused region 7 is formed on an N-type semi coneductor substrate 1 between a P-type transistor forming region 3 and an N-type transistor forming region 4 and facing the first P-type diffused region 5a-5d. The second P-type diffused region 8 is formed on a P-type well region 2 between the P-type transistor forming region 3 and the N-type transistor forming region 4 and facing the first N-type diffused regions 6a-6d. Polycrystalline silicon layers provided above the areas between the respective first P-type diffused regions 5a-5d are extended into the area between the P-type well region 2 and the second N-type diffused region 7 to provide polycrystalline silicon gates 10a-10c. Polycrystalline silicon layers pro vided above the areas between the respective first N-type diffused regions 6a-6d are extended into the area between the N-type semiconductor substrate 1 and the second P-type diffused region 8 to form polycrystalline silicon gates 10d-10f.