| 摘要 |
PURPOSE:To decrease leaking, by forming an isolating layer in a P-type Si substrate, on the surface of which SiO2 and first poly Si layer having large impurity diffusion are laminated, coating the surface by a second Poly Si layer, etching and removing the bottom of a groove, and diffusing B only into the Si substrate on the side of N channel from the wall of the groove. CONSTITUTION:SiO2 2 and poly Si 16 are laminated on a P-type Si substrate 1. RIE of the substrate is performed, and a vertical groove 5 is formed. Poly Si 17 is overlapped. RIF is carried out, and the layer 17 at the bottom surface is removed. The surface is covered by CVD SiO2 18. Poly Si 7 is overlapped, and a resin mask is applied. Then etch back is performed. The poly Si is made to remain only in the groove 5. Thereafter, the SiO2 and the poly Si 16 in the P-ch region are selectively etched and removed. P ions are implanted and annealing is performed. Thus an N well 8 is formed. The poly Si 18 remaining on the surface is etched and removed. B ions are selectively implanted in the poly Si 16. Heat treatment is performed, and B is diffused 19 from the poly Si 17 on the side wall of the groove. The poly Si 16 is etched and removed. A field oxide film 9, a gate oxide film 10, a gate electrode 11, N<+> source and drain 12, an interlayer insulating film 13 and a wiring 14 are formed as usual. Leak currents are suppressed by the layer 19, and the CMOS having a high density can be formed. |
