发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce element effective area and to improve high-resistance layer controllability by a method where in a lamination constituted of a tantalum film to serve as a stopper and a tantalum oxide film to serve as a high- resistance layer is formed on a part of the source or drain electrode of a Schottky gate FET. CONSTITUTION:On a semi-insulating GaAs substrate 1, an n-type enhancement layer 2 is formed, for the building of a gate electrode 5, source and drain ohmic electrodes 3 and 4, for a Schottky gate FET. An insulating film 6 is formed made of CVD-SiO2 or the like, whereafter an opening is provided in the insulating film 6 for the source ohmic electrode 3. Next, the entirety of the substrate 1 is covered with a tantalum oxide film (element high-resistance section) 8. The formation of the required thickness of a tantalum film 7. A source electrode 10 and a drain electrode 11 are then formed respectively by photolighography and by reactive dry etching. This design reduces element effective area and improves the controllability of its high-resistance layer.
申请公布号 JPS61255051(A) 申请公布日期 1986.11.12
申请号 JP19850097102 申请日期 1985.05.08
申请人 NEC CORP 发明人 KAMITAKE KAZUTAKA
分类号 H01L27/095;H01L21/822;H01L27/04;H01L27/06 主分类号 H01L27/095
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