| 摘要 |
<p>PURPOSE:To optimize the rate of occupation of a main bus by each CPU by providing a main bus selection control circuit for synchronizing processes of respective CPUs of a dual processor system. CONSTITUTION:A main CPU51 and a slave CPU52 output signals 63 and 64 for requesting the occupation of the main bus 57 to the main bus selection control circuit 53, and the priority of the bus occupation is determined on the basis of previously set numerals. Consequently, it is decided which of the CPUs 51 and 52 occupies the bus 57. Consequently, a wait signal 61 or 62 is inputted from the circuit 53 to the CPU51 or 52 which is disallowed to occupy the bus 57 and the CPU which inputs the signal is put in a wait state. Further, the circuit 53 controls the connection and disconnection between a bus 56 and the main bus 57, and a bus 55 and the main bus 57. Thus, the circuit 53 is provided to optimize the occupation rate of the main bus 57 by each CPU.</p> |
