Logic circuit having a test data loading function.

摘要

A logic circuit having a test data loading function, comprising at least one J-K flip-flop (1). Each J-K flip-flop includes a test data latching logic circuit (2). In response to an enable signal (E), test data (D) is selected in place of the usual J and K input data to be latched. In a complex logic circuit including such flip-flops, a test can be effected in a short time.