| 摘要 |
PURPOSE:To obtain a filter with stable operation and less power consumption by providing M-stage of shift registers reading an input data string in a speed being N times of the bit repetition, a weighting means with respect to the output of the shift registers and an adder means. CONSTITUTION:The M-stage shift registers 4 reading an input data string 100 in a speed being N times of the bit repetition, the weighting circuits 9 controlling the polarity of a constant in binary representation by the output of each stage and the digital adder circuit 10, and each weighting circuit 9 outputs a code of each bit of constant circuit 11 as it is when an input 102 in logical '0' and outputs a complement when logical '1'. The arithmetic time of each adder of the circuit 10 is selected to be finished within one period of the clock signal so as to attain the arithmetic processing in real time. Since all the weighted outputs of each tap are added by the digital processing, stable waveform shaping with high accuracy is attained. Further, each constituting circuit is realized by gate arrays and the power consumption is less.
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