| 摘要 |
PURPOSE:To execute highly speedy access by providing a timing generating circuit with a Y system to form a series of the action timing signal by a chip selecting signal and an X system to form a series of the action timing signal by the signal for making invalid the indicating level of the chip non-selecting condition for a short time. CONSTITUTION:A chip selecting signal, the inverse of CE from the external terminal is supplied through a Y system timing signal generating circuit Y-TG and a pulse width deciding circuit to an X system timing generating circuit X-TG. The pulse width deciding circuit inputs the delaying signal through the signal, the inverse of CE and a delaying circuit DL to an AND gate circuit G and forms the deciding signal to make invalid the chip selecting signal, the inverse of CE made into a high level for a comparatively short period. When the page mode is executed, the period of the high level of the chip selecting signal, the inverse of CE is made shorter than the delaying time, and the X system timing signal maintains the previous condition, namely, maintains the selecting action of one word line. When a Y system selecting circuit is once reset and the signal, the inverse of CE comes to be a low level, the selecting action of the data line in accordance with the address of the address signal synchronized and supplied to it is executed.
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