| 摘要 |
An algorithmic analog-to-digital and digital-to-analog converter 10 combines the techniques of switched capacitor cyclic conversion by using first and second amplifiers 31, 32 with capacitors C1, C1', C2, C2', C3, C3', C4, C4', C5, C5' communicating with the inputs of said amplifiers 31, 32 and between the inputs and outputs of said amplifiers 31, 32, and the techniques of reference voltage refreshing. The performance of the converter 10 is capacitor ratio-independent. Because of the ratio-independent aspect, very small component values can be used, and as a result, the die area required for the circuitry can be quite small.
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