| 摘要 |
PURPOSE:To reduce load to individual CPU and resident bus by dividing contents of process into receiving process and main control for other data processing, and providing a CPU for each process. CONSTITUTION:A packet received is controlled by a receiving HDLC circuit 4 and a RxDMAC circuit 12 to be transferred to a memory 3 with DMA operation. The DMA operation is controlled by a sub CPU 11. The packet which was transferred by the memory 3 is processed by a main CPU 1a. This packet processed is DMA transferred from the memory 3 to a sending HDLC circuit 5 for transmission under the control of a DMAC circuit 2. It is sent from the sending HDLC circuit 5 as a packet in the specified format.
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