| 摘要 |
PURPOSE:To correspond to both modes of NTSC, and scramble without using a delay correcting circuit of analog by operating a whole of the system as a PLL system using a digital synchronous signal in a scramble mode and as the PLL system using a burst signal in the NTSC mode. CONSTITUTION:PLL arithmetic circuits 120, 120 used in the descramble device have PLL error arithmetic circuits 121, 122 correspondingly to a scramble mode, an NTSC mode respectively and comprises a change over circuit 123 for changing over and outputting in accordance with a mode outputs of the error arithmetic circuits 121, 122 and a loop filter 124. Respectively calculated error signals Es, En are supplied together to the change-over circuit 123. The change-over circuit 123 selects Es during the scramble mode in accordance with a mode change over signal 53, and En during the NTSC mode, respectively and supplies as an output signal 125 to the loop filter 124. The loop filter 124 smoothes the inputted error signal 125 and supplies as a phase error signal 15 to a D/A converting circuit. |
