| 摘要 |
PURPOSE:To display analogically the result to count with simple constitution by providing an adder circuit, two reset means interlocking with each other and a circuit holding a maximum value of the addition voltage of the adder circuit and using the output of the said holding circuit as the 2nd input of the adder circuit via an LPF. CONSTITUTION:After reset is finished by the switching of interlocking switches 105, 110, the 1st error detection pulse having a voltage Vp is inputted to the adder circuit 101. In this case, since the output of the LPF 102 is 0, the voltage of the said pulse appears as it is at the output of the circuit 101 and a capacitor 104 of the peak hold circuit 107 is charged and held up to a voltage Vs being the subtraction of a forward voltage VDS of the diode 103 from the voltage Vp. Since the LPF 102 has a slow leading characteristic, the output voltage of the circuit 107 approaches gradually the Vs. The output is fed back to the circuit 101. Then the output voltage of the circuit 107 rises as Vs, 2Vs, 3Vs... at each generation of the error detection pulse. The output is displayed analogically on a voltmeter 116 via a peak meter circuit 115.
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