发明名称 VECTOR INSTRUCTION PROCESSOR
摘要 PURPOSE:To speed up instruction processing by inhibiting reading of a corresponding vector factor while a mask bit read out in such a way that mask bit reading proceeds the reading of the corresponding vector factor is indicating the arithmetic to be restrained. CONSTITUTION:At the time of starting a vector instruction, a mask vector address register 12, an inter-vector factor distance registers 41-43 and vector factor registers 49-51 are initialized. The value of an address addition value register 13 is added to the value of the register 12 so as to read out the mask vector from a memory device 2 and stored in a mask vector register 32. A priority encoder 33 counts arithmetic inhibiting bits from the top of the mask vector until the initial arithmetic indicating bit can be found. A multiplying circuit 45 multiplies an inter-vector factor distance by the number of arithmetic inhibiting bits, an address adder circuit 53 adds a difference address to read the vector factor from a memory device 5. The read-out vector factor is transferred to an arithmetic device, thereby speeding up the instruction processing.
申请公布号 JPS61251960(A) 申请公布日期 1986.11.08
申请号 JP19850065397 申请日期 1985.03.29
申请人 NEC CORP 发明人 FUKUZAWA HAJIME
分类号 G06F17/16 主分类号 G06F17/16
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