| 摘要 |
PURPOSE:To adjust a generating time of one vertical synchronous signal so as to make a relative phase of the vertical synchronous signal of the first field and the vertical synchronous signal of the second field 1/2H by providing a vertical synchronous signal amplitude setting means. CONSTITUTION:A vertical synchronous signal amplitude setting circuit 4 comprises of an FF 20, a preset counter 22 and an AND gate 24. By a carry output of the counter 22, the FF 20 is reset the preset data is preset to the counter 22 by an output of a monostable multivibrator 10 and by an output of the AND gate 24, the counter 22 is brought into an enable condition, and an amplitude of the output vertical synchronous signal is set to 190mus. According to this, with respect to an original vertical synchronous signal, a generating timing of the output vertical synchronous signal of one field can be adjusted and a relative phase of the output vertical synchronous signal of the first field and the output vertical synchronous signal of the second field can be precisely set to 1/2H.
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