| 摘要 |
PURPOSE:To attain good scanning by generating an image scan clock the frequency of which changes consecutively according to the change of scanning speed. CONSTITUTION:By switching the ratio of dividing of a divider 12, phase difference occurs between frequency of a position control clock and a clock CLA, causing frequency of an output clock from a voltage control oscillator 22 to be changed consecutively and simply. Thus, changing the ratio of dividing of the divider 12 in steps can change the frequency of the image scan clock consecutively. Since a control circuit 16 generates a clock K which causes a U/D counter to output the preset value of the ratio of dividing of the divider 12, a signal EN to allow counting, and a signal U/D for mode measurement, the frequency of the image scan clock generated from the oscillator is set to be nearly equal to the frequency change caused by the change of scan speed.
|
