发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To use effectively the area of a RAM by using duplicate addresses to access a ROM at a read time and access the RAM at a write time and rewriting contents of a register to access only the RAM at a read time as well as a write time. CONSTITUTION:Duplicate addresses 0000H-07FFH are allocated to a RAM2 and a ROM3. An output 4000 of an address decoder 4 for the first read is ''1'' because address 0000H is included in the ROM3, and an output 5000 of a control register 5 is ''1'' by initialization, and an R/W output 1002 of a CPU1 is ''1'', and therefore, an output 6000 of an AND gate 6 is ''1''. The output 6000 is supplied to an enable terminal CS of the ROM3 to enable the ROM3. A memory access enable signal 7000 to the RAM2 is inhibited from being supplied to the RAM2, and the RAM2 is not enabled. Only the ROM3 is operated as long as the CPU1 reads 0000H-07FFH.
申请公布号 JPS60189044(A) 申请公布日期 1985.09.26
申请号 JP19840044420 申请日期 1984.03.08
申请人 NIPPON DENKI KK 发明人 TOMIOKA HIDEHIRO
分类号 G06F12/06;(IPC1-7):G06F12/06 主分类号 G06F12/06
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