发明名称 ERROR CHECK BIT COMPRESSION SYSTEM
摘要 PURPOSE:To save the number of jumpers by utilizing that the number (n) of registers written at the same time is smaller than the number N of registers, using a selector and selecting and transferring an output to the n-set. CONSTITUTION:A register 1 comprised of N words each constituting [8-bit + check bit (P)] is divided into two LSIs and 0-3 bits exist in the LSI #1 and 4-7 bits exist in the LSI #2. When n-set of the registers (1<=n<N) are written at the same time to the registers (1-N), a signal designating the n-set of the registers is set to respectively the latch (L) 4 of the LSIs #1, #2 and after the check bit to the n-set of the registers subjected to write is produced by each check bit generation circuit 2, the selector (SEL) 3 selects only the n-set of check bits and transferred on an interface line (IFL).
申请公布号 JPS61250743(A) 申请公布日期 1986.11.07
申请号 JP19850092512 申请日期 1985.04.30
申请人 FUJITSU LTD 发明人 UEMOTO SHIGEMI;UEDA KOICHI
分类号 G06F11/08;G06F11/10;G06F11/22 主分类号 G06F11/08
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