| 摘要 |
<p>PURPOSE:To generate a correct internal timing even when the relation of phase is changed between an internal clock signal and an internal clock signal. CONSTITUTION:An external clock signal CLK 1 is inputted to a D input terminal of the 1st D flip-flop (DFF) 11. The DFF 11 holds the state of the CLK 1 syn chronously with the internal clock signal CLK 2. The 2nd DFF 12 holds the state of an output signal of the 1st DFF 11 synchronously with the CLK 2. A counter 13 is set initially synchronously with the output signal of the 2nd DFF 12 and counts the internal clock signal CLK 2. When an output signal of the 2nd DFF 12 and a count end signal of the counter 13 are inputted respec tively to a NAND gate 14 and an AND gate 15, the output signal of the 1st DFF 11 is not inputted to the 2nd DFF 12. The counter 13 controls the internal timing depending on the count of the counter 13.</p> |
