| 摘要 |
PURPOSE:To realize an adder/subtractor with the number of logical stages by incrementing/decrementing a high-order from a bit where a longer binary- data is subject to addition/subtraction depending on the presence of a carry output of an adder having a shorter bus width in two binary data. CONSTITUTION:Bit widths existing in both an addend A and an adder B are taken respectively as A', B' and the high-order bit of the addend A is taken as A''. The part A' of an addend register 10 and a part B' of an adder register 20 are added by an adder 3 and an exclusive OR between the carry signal C at that time and a sign bit Sb of the adder register 20 is operated by a circuit 6, and increment is applied to the part A' with C=1, Sb=0 and decrement is applied with C=0, Sb=1. In case of the increment, when lower-order bits than the said bit are all 1, the carry signal C=1 is propagated and the first 0 is set to 1 and in case of the decrement, when lower-order bits than the said bit 1 are all 0, the carry signal C=0 is propagated and the 1st 0 is set to 1. |
