发明名称 |
MOS TRANSISTOR CIRCUIT WITH BREAKDOWN PROTECTION |
摘要 |
A protected MOS transistor circuit includes a first input (or output) MOS transistor (1) and a protective circuit (10) including a second depletion mode MOS transistor (TrP) having a drain-source current path connected between ground and the gate of the MOS transistor and arranged to prevent breakdown of the gate of the protected MOS transistor when power is off as a consequence of stray voltages when power is off. A substrate voltage generating circuit is arranged to generate a substrate bias voltage which is applied to the substrate of the second MOS transistor when power is on so as to alter its threshold voltage, causing the transistor to become non-conductive. |
申请公布号 |
DE3175407(D1) |
申请公布日期 |
1986.11.06 |
申请号 |
DE19813175407 |
申请日期 |
1981.06.17 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ASANO, MASAMICHI;IWAHASHI, HIROSHI;KOBAYASHI, ICHIRO |
分类号 |
H03F1/52;H01L27/02;H01L27/06;H01L29/78;H02H7/20;H03F1/42;H03K17/0812;H03K19/00;H03K19/003;(IPC1-7):H01L27/04 |
主分类号 |
H03F1/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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