| 摘要 |
PURPOSE:To attain a pulse delay time control by a single control voltage by using a MOS transistor (TR) so as to change an output line resistance value on output lines of a half of even number of lines when a pulse edge of an input pulse is transmitted on the lines. CONSTITUTION:MOS TRs 21 and 22, 31 and 32, and 41 and 42 form respectively the inverter of complementary MOS. Since the quantity of the conductive resistance value of a conductor path is controlled by a voltage 6 fed to gate terminals of N-MOS TRs 22, 23, the output line resistance is made variable when the N-MOS TR 22 or 32 is turned on with an inverter 2 or 3 at low level output state. Since the conductive resistance is lowered more as an applied voltage 6 to the gate of the N-MOS TRs 23, 33 gets higher, the variable control of the delay time decreasing/increasing t1, t2 is attained by increasing or decreasing the applied voltage so as to make the gradient of the discharging curve steep or gentle. |
